Generally, a ring shaped stacked capacitor cell is manufactured as shown in FIG. 1 and as described hereinafter. Silicon oxide layer 2 and silicon nitride layer 3 are successively deposited upon silicon substrate 1, and a contact hole is opened by a photo-etching process (FIG. 1(a)). Then as shown in FIG. 1(b), polysilicon layer 4 is deposited upon silicon nitride layer 3, and then another silicon oxide layer 5 is deposited thereon. Thereafter, silicon oxide layer 5 is patterned to be formed as an etch mask for the etching of polysilicon layer 4, and then polysilicon layer 4 is partially etched using the oxide mask as shown in FIG. 1(c).
Then, as shown in FIG. 1(d), silicon oxide layer 6 is deposited, and then silicon oxide layer 6 is etched back to form silicon oxide side wall 7.
Next, as shown in FIG. 1(e), a polysilicon layer is deposited and etched back to form polysilicon side wall 8 in order to utilize it as a ring shaped capacitor storage electrode.
Then, as shown in FIG. 1(f), silicon oxide layer 5 and side wall 7 are subjected to a wet etch within an HF buffering solution, thereby forming capacitor storage electrode 9. In the above process, silicon nitride layer 3 serves as an etch stop layer in the polysilicon etch process.
Finally, as shown in FIG. 1(g), dielectric layer 10 is formed on storage electrode 9, and cell plate 11 is formed on dielectric layer 10, thereby completing the process for forming the capacitor.
In the above described conventional capacitor forming process, it is very difficult to etch the polysilicon layer partially to form a thin polysilicon element of a predetermined thickness as in the step of FIG. 1(c). Further, with the main and ring electrodes, the increase of the capacitance is very limited, thereby making it difficult to form a high density memory cell.